Semiconductor fabrication is one of the most complex manufactur-ing processes. From raw silica to packaged integrated circuits (IC), semiconductor fabrication involves hundreds of steps performed on a variety of types of equipment, many taking place in a clean-room environment. Yields—the percentage of product that passes all tests and makes it into the field—strongly depend on sevearl factors, most of which are extremely difficult to control. With all of these complexities, isolating and reducing variables is a
monstrous task—one that is perfect for Six Sigma.
Increasingly, Six Sigma tools are used in the semiconductor industry to ensure consistency, predictability and, ultimately, optimality of process out-puts. Coupled with improved control, optimal performance and increased throughput, many semiconductor companies have enjoyed substantial savings by applying Six Sigma.
In this case study, we present the results of the application of Six Sigma in a semiconductor manufacturing company interested in increasing throughput and yield of its wafer-sawing (dicing) process. This step at the end of wafer fabrication is the most critical in determining the throughput and overall yield of the process.
A manufacturing company had established that among many serial processes, the wafer-sawing process was a yield-limiting process with typical batch process yields of about 65%. A batch is 25 wafers of 6-inch diameter, with each wafer having about 10,000 semiconductor dies. This yield-limiting process presented an excellent opportunity for a Six Sigma define, measure, analyze, improve and control (DMAIC) approach for optimizing the process, as well as the yield of this operation.
The purpose of the wafer-sawing
process is to realize the estimated quantity of singulated dies coming
from the processed wafers. Low yields at this stage of the process dictated that
the upstream wafer fabrication facility
had to process more wafers to account for the cost of poor quality at wafer sawing and compensate for the current yield of about 65%. Optimizing the process would minimize the cost of poor quality and streamline the capacity plan of the wafer fabrication processes.
Initial assessment of the situation identified that in this instance, the failure mode causing the issue was chipouts, or edge fragmentations, on the edges of the semiconductor dies (Figure 1).
The presence of chipouts can be a source of physical die cracking or total breakage at the end of line-assembly processes. During assembly or in-field
Table 1. Chipout data before and after optimization
|Metric||Before optimization||After optimization|
|(Figure 2)||(Figure 16)|
operation, microcracks can damage the circuit region of an IC die, which can lead to electrical failures at final inspection or reliability failures in the field.
Initial investigation of operations revealed the process had a statistical process control (SPC) and data-tracking system in place, thanks to the wafer sawing tool’s in-process kerfwidth (the width of the slot the blade cuts in the material) and chipout moni-toring camera. Although chipouts were monitored, specifications for process definition did not exist. This prompted discussions with product engineering as to the appropriate specifications for the chipout.
For the design of the chips, an upper specification limit (USL) of 0.5 millimeters for the chipout was developed by product engineering. Baseline data were collected, and the histogram in Figure 2 (p. 29) presents the snapshot of process performance based on the chipout data as compared to the newly implemented specifications. This became the starting point for this study.
Also discovered during this define and data-bench-marking phase was that operations used two different wheel mounts. The original one was relatively new, and during operation it was replaced with an older one. Operations did this to equip another wafer saw for production use while we experimented on the current one. This revelation made us understand the deeper effects of the wheel mount condition in relation to wheel mount planarity. The resulting his-togram is of a bimodality type, as shown in Figure 2.
Separate product performance studies confirmed that chipouts of less than 0.5 millimeters had no impact on product reliability, nor did they cause die cracking or breaking during the assembly processes. Having established this, the USL is maintained as the working envelope for the process.
The objectives of this study at this stage were then formally defined:
- To understand the process factors influencing chipouts.
- To find the best settings of these factors to get the lowest chipouts possible within the fastest time allowable.
Figure 3. GR&R study
|Total gage R&R||0.0000108||0.09|
|study Var||%Study Var|
|Source||StdDev (SD)||(6 * SD)||(%SV)|
|Total gage R&R||0.003288||0.019731||2.99|
- To optimize the process with respect to a USL of 0.5 millimeters for chipouts.
The measurement phase primarily involved the veri-fication of the measurement precision and accuracy of the in-process chipout monitoring camera of the wafer saw. To that end, a gage repeatability and repro
Increasingly, Six Sigma tools are used in the semiconductor industry to ensure
consistency, predictability and, ultimately, optimality of process outputs.